This invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) in which the gate electrode is essentially a doped polysilicon layer with an impurity concentration gradient in the thickness direction and a method of producing the MOSFET. The impurity concentration gradient in the polysilicon gate electrode is for reducing the electric field on the gate oxide film. On one semiconductor chip, MOSFETs according to the invention can be used in both a high-speed circuit to be operated at a low supply voltage and a high-voltage interface without differentiating the thickness of the gate oxide film.
Device dimensions of MOSFETs have been scaled down for improvements in performance including enhancement of operation speed. According to the scaling rule on MOSFETs, for a K-fold increase in operation speed both the gate length and the gate oxide film thickness should be reduced to 1/K. However, in view of reliability of the device it is impermissible to freely intensify the electric field acting on the gate oxide film. Therefore, when the gate oxide film thickness is reduced to 1/K it is necessary to lower supply voltage to 1/K.
With the developments of microfabrication techniques, MOSFETs of each generation of technology are smaller in size than MOSFETs of the previous generation of technology. However, if different supply voltages are actually employed for devices of different technology generations there arises a problem in a system in which devices of different generations coexist. That is, system components or sub-systems that are operated at different supply voltages cannot be directly connected with each other because of mismatching of input-output levels. To resolve this problem, it is necessary to supplement the system with an extra apparatus or circuit such as a level shifter or to provide a buffer circuit for matching input-output levels within the system.
For example, let's suppose that an IC including a MOS logic circuit which is operated at a supply voltage of 3.3 V is to be directly connected with another semiconductor circuit operated at a voltage of 5 V. In the low-voltage logic circuit the thickness of the gate oxide film must be 10-12 nm, but an output part of the IC needs to include a buffer circuit using output MOSFETs in which the gate oxide film thickness is about 15 nm. That is, it is necessary to form two gate oxide films different in thickness on a single substrate. So, two different oxidation steps are needed, and two photolithographic steps are needed to select the areas for the respective gate oxide films. Naturally the fabrication process becomes very complicated.
Meanwhile, JP-A 5-55560 (1993) proposes to substantially reduce the intensity of electric field acting on the gate oxide film of a MOSFET by evading direct application of supply voltage to the gate oxide film. More particularly, the proposal is a polysilicon (polycrystalline silicon) gate electrode having a two-layer structure with different impurity concentrations.
FIG. 5 of the accompanying drawings shows a MOSFET according to JP-A 5-55560. For example, the MOSFET in FIG. 5 is a p-channel MOSFET. A gate oxide film 52 lies on an n-type semiconductor substrate 50, and p.sup.+ -type source and drain regions 54 and 56 are formed in the substrate 50. A gate electrode 58 on the gate oxide film 52 is formed of doped polysilicon and has a two-layer structure consisting of a lower polysilicon layer 58a in which the impurity concentration is relatively low and an upper polysilicon layer 58b in which the impurity concentration is relatively high. In FIG. 5, a drain voltage V.sub.D, which is a positive and relatively high voltage, is applied to the drain region 56. The gate electrode is negatively biased by a gate voltage V.sub.G. The source region is kept at ground potential. In this state, a depletion layer 60 is created in the lightly doped polysilicon layer 58a in a region close to the drain region 56 by the action of the high drain voltage V.sub.D. As a result, the potential difference between the drain and gate, V.sub.D +V.sub.G, is divided by a capacitance of the gate oxide film 52 and another capacitance of the depletion layer 60, and therefore an effective electric field acting on the gate oxide film 52 is reduced.
However, this two-layer structure of the polysilicon gate electrode has disadvantages with respect to the fabrication process. It is necessary to perform two polysilicon deposition steps and two doping steps. Besides, when the lower polysilicon layer 58a is formed by chemical vapor deposition as is usual, it is necessary to deposit polysilicon at least to a thickness of about 50 nm for accurately controlling the thickness, though a thinner layer is desirable. As a result, the total thickness of the two polysilicon layers is liable to become greater than a desirable thickness a gate electrode, and therefore difficulties arise in precise patterning of the polysilicon layers. Furthermore, in the case of fabricating MOSFETs shown in FIG. 5 and MOSFETs of a different gate electrode structure to be operated at a relatively low supply voltage on a single substrate, different process steps are needed for the two kinds of MOSFETs.